Computer System Architecture

In this section, we explore how a computer system handles input/output (I/O) processes. I/O processes enable interaction with external devices like keyboards, monitors, and printers. There are three main methods for handling I/O processes: busy waiting, interrupts, and direct memory access (DMA).

I/O Process Handling Methods

Busy Waiting

• Description: The CPU continuously checks the status of the I/O device until it is ready, leading to inefficient use of CPU time.
• Other Names: Busy-looping, polling I/O, or spinning.

Interrupt-Driven I/O

1. Device Controller:

   • Components:
     • Local Buffer Register: Stores data for transfer.
     • Special Usage Register: Used by the CPU to write commands and read status.

2. Processing Flow:

   • The CPU issues an I/O command to the device controller's Special Usage Register.
   • The CPU continues executing other instructions.
   • When the device is ready, it sends an interrupt signal to the CPU.
   • The CPU stops its current execution, saves the context, and jumps to the Interrupt Service Routine (ISR) using the interrupt vector table to locate the ISR.
   • The ISR transfers data from the local buffer registers to main memory.
   • The CPU restores the context and resumes the interrupted process.

3. Key Points:

   • Interrupt Vector: Contains the ISR address and interrupt ID, used by the CPU to find the corresponding ISR when an interrupt occurs.
   • Interrupt Priority: Determines which interrupt to handle first when multiple interrupts occur, typically based on a priority scheme.
   • Context Switch: The CPU saves the current process's context and loads the ISR's context upon an interrupt, then restores the context after ISR execution.

4. Types of Interrupts:

   • External Interrupts: Generated by hardware devices. Examples include:
     • Machine Check Interrupt: Indicates hardware failure or error (e.g., memory parity error).
     • I/O Interrupt: Signals that an I/O operation is complete or needs attention (e.g., keyboard input, printer ready).
     • Device Fault Interrupt: Indicates a fault in a device requiring attention.
   • Internal Interrupts (Traps): Generated by the CPU when it detects an error or specific condition during instruction execution. Examples include:
     • Overflow: Triggered when arithmetic operations exceed the CPU's capacity.
     • Arithmetic Operation Error: Triggered by errors like divide by zero.
   • Software Interrupts: Generated by software instructions. Examples include:
     • System Call (Supervisor Call): Allows user programs to request OS services.
     • Trap Instruction: Used for debugging and error handling.
     • Exception: Handles unexpected conditions during program execution (e.g., illegal instruction).

5. OS Handling an Interrupt:

   • The OS acquires CPU control.
   • Saves the current process's context and registers to the stack.
   • Retrieves the interrupt vector and finds the corresponding ISR.
   • Executes the ISR.
   • Restores the context and resumes the interrupted process.

Direct Memory Access (DMA)

DMA reduces CPU involvement by allowing devices to transfer data directly to and from memory.

1. DMA Controller:
   • Components: Holds source and destination addresses and transfer length in registers.
2. Cycle Stealing: The DMA controller shares the memory bus with the CPU. When the DMA controller needs to transfer data, it "steals" cycles from the CPU to access the memory, allowing data transfer between I/O devices and memory without CPU intervention.

Real-World Example

Consider downloading a large file from the internet while working on a document:

• Busy Waiting: The CPU constantly checks if the file download is complete, slowing down document editing.
• Interrupt I/O: The CPU receives an interrupt when the download progresses or completes, allowing uninterrupted document editing.
• DMA: The network card transfers the file directly to memory using DMA, so the CPU can focus on document editing with minimal interruption.

I/O Operation Management

Waiting for I/O to Complete (Polling, Synchronous I/O)

• Wait Instruction: The CPU idles until the I/O operation is finished.
• Busy Waiting (Polling): If no wait instruction exists, the CPU continuously checks the I/O status, wasting resources.
• Advantages: The OS knows which device caused the interrupt as only one request is handled at a time.
• Disadvantages: Prevents parallel I/O operations, reducing efficiency.

Starting I/O and Returning Control to User Program (Asynchronous I/O)

• After initiating the I/O, control returns to the user program.
• The user program can request the OS to wait for I/O completion via another system call.
• The OS manages multiple I/O requests using a Device Status Table to track each device's status.

Dual Mode Operation

Computer systems operate in two modes: User Mode and Kernel Mode (Supervisor Mode, System Mode, or Privileged Mode). These modes provide hardware protection and isolation between user programs and the operating system. The computer hardware includes a mode bit to indicate the current mode: 0 for Kernel Mode and 1 for User Mode.

Why Dual Mode?

• Protection: Ensures user programs cannot interfere with the operating system or other programs. This isolation prevents user errors from affecting other users. Privileged instructions can only be executed in Kernel Mode, maintaining system stability and security.
• Resource Management: Allows the operating system to control hardware resources and manage system operations effectively. Kernel Mode provides direct access to hardware and system resources, enabling the OS to perform critical tasks like memory management, process scheduling, and I/O operations.

Protection Mechanisms in Hardware

1. I/O Protection: Prevents user programs from executing illegal I/O instructions.
2. Memory Protection: Prevents user programs from accessing kernel memory by enforcing memory boundaries.
3. CPU Protection: Prevents user programs from monopolizing the CPU by enforcing time limits (Timer).

I/O Protection

• Purpose: Ensure that only the kernel can execute I/O instructions to prevent unauthorized access to I/O devices by user programs.
• Mechanism: The operating system restricts I/O instructions to Kernel Mode. Any attempt by a user program to execute these instructions triggers an exception, switching control to the OS.
• Preventing Kernel Mode Hijacking: Protect the vector table from being modified by user programs to prevent control hijacking.

Memory Protection

Memory protection ensures that user programs do not interfere with the operating system (OS) or other user programs. This is achieved through the use of specific hardware mechanisms.

1. Between User Programs and OS Memory

   • Fence Register: A boundary register that separates user program memory from OS memory.
   • Function: If a user program attempts to access memory below the fence register (which is reserved for the OS), the CPU generates an interrupt (trap) to the OS, preventing unauthorized access.

2. Between Jobs

   • Base Register: Contains the smallest legal physical memory address for a user program.
   • Limit Register: Specifies the size of the memory range allocated to the user program.
   • Function: If a user program tries to access memory outside its allocated range (as defined by the base and limit registers), the CPU generates an interrupt (trap) to the OS. These registers ensure each program operates within its assigned memory space and can only be modified by the OS in kernel mode.

CPU Protection

CPU protection ensures that no single user program can monopolize the CPU, allowing fair allocation of processing time to all programs. One of the primary mechanisms to achieve this is through the use of a Timer.

1. Setting the Timer: Before the operating system hands over control to a user program, it sets the timer to generate an interrupt after a specified time interval.
2. Execution and Monitoring: The user program executes its tasks, and the timer counts down during this period.
3. Timer Interrupt: If the user program does not complete its execution within the allotted time, the timer reaches zero and generates a timer interrupt.
4. Returning Control: The timer interrupt signals the CPU to stop the current user program and switch control back to the operating system.

Privileged Instructions

1. Set/Change Timer
2. Modify Memory Management Registers
3. I/O
4. Halt the CPU
5. Disable Interrupts
6. Switch from User to Kernel Mode

Multi-Processor Systems

Multi-processor systems have tightly coupled processors sharing buses, memory, and devices.

Advantages:

1. Increased Throughput: Multiple processors handle tasks simultaneously.
2. Fault Tolerance: System remains operational even if one processor fails.

Symmetric Multiprocessing (SMP): Equal processors share the workload and memory, requiring balanced I/O control.

Asymmetric Multiprocessing (AMP): One master processor controls the system, with simpler design but less efficiency compared to SMP.

Conclusion

In this section, we explored the architecture of a computer system, focusing on input/output (I/O) processes and how they are managed. We examined three main methods for handling I/O: busy waiting, interrupts, and direct memory access (DMA). Each method offers different levels of efficiency and CPU involvement.

We also delved into dual mode operation, which ensures protection and separation between user programs and the operating system through user mode and kernel mode. Additionally, we covered essential hardware protection mechanisms such as I/O protection, memory protection, and CPU protection, emphasizing the importance of privileged instructions.

Lastly, we touched on multi-processor systems, highlighting the differences between symmetric and asymmetric multiprocessing, and their respective advantages in terms of throughput and fault tolerance.

Nice! We have covered the basics of computer system architecture. Next, we will explore the structure and components of operating systems.

Further Reading